1. Field of the Invention
The present invention relates to a probe card, and more particularly, the present invention relates to a probe card used to test electrical characteristics of chips on a semiconductor wafer.
A claim of priority under 35 U.S.C. § 119 it made to Korean Patent Application 2003-3514 filed on Jan. 18, 2003, the entire contents of which are hereby incorporated by reference.
2. Description of the Related Art
A semiconductor test apparatus, which is used to test electrical characteristics of chips manufactured on a wafer, typically includes a tester, a performance board, a probe card, a chuck, and a prober.
The probe card of the semiconductor test apparatus is made up of a stack of alternately arranged signal printed circuit boards and ground printed circuit boards. The signal printed circuit boards are for applying power supply signals, command and address signals, and data signals, and the ground printed circuit boards are for applying ground signals.
Rather than individually testing chips one at a time, the conventional semiconductor test apparatus is capable of testing a plurality of chips at the same time. However, as explained below, the conventional probe card suffers from ground noise which can result in erroneous test results.
FIG. 1 is a block diagram illustrating a conventional semiconductor test apparatus. The semiconductor test apparatus of FIG. 1 includes a tester 10, a performance board 12, a probe card 14, a chuck 20, and a prober 22. The performance board 12 includes an upper board 12-1 and a lower board 12-2.
In FIG. 1, reference numeral 16 denotes a probe needle which is fixed to the probe card 14, and reference numeral 18 denotes a wafer 18 loaded onto the chuck 20.
The functioning of the components of the semiconductor test apparatus of FIG. 1 are explained below.
The tester 10 outputs a test signal and determines whether or not the chips of the wafer 18 are operating normally based on a received signal corresponding to the output test signal. The performance board 12 transmits the signal output from the tester 10 to the probe card 14, and transmits a signal received from the probe card 14 to the tester 10. The probe card 14 transmits a signal received from the performance board 12 to pads of the wafer 18 through the needle 16, and transmits a signal outputted from the pads of the wafer 18 through the needle 16 to the performance board 12. The chuck 20 is attached to the prober 22 and is used to mount the wafer 18. The prober 22 moves the chuck 20 to a desired location under control of the tester 10.
As shown in FIG. 1, the tester 10 generates power supply signals P1 and P2, a power ground signal PG, command and address signals C1 to Cm, ground signals CG1 to CGm of the respective command and address signals C1 to Cm, data input/output signals IO1 to IOn, and ground signals G1 to Gm of the respective data input/output signals IO1 to IOn. The signals generated from the tester 10 are applied to the upper board 12-1 of the performance board 12 through signal lines PSL1, CSL1 and IOSL1, and signals outputted from the upper board 12-1 of the performance board 12 are transmitted to the lower board 12-2 through signal lines PSL2, CSL2 and IOSL2. The signals outputted through the lower board 12-2 of the performance board 12 are transmitted to the probe card 14 through signal lines PSL3, CSL3 and IOSL3. That is, each of the signals outputted from the tester 10 is transmitted to the probe card 14. Of course, the ground signals CG1 to CGm among the signals outputted from the tester 10 can be simultaneously transmitted through a single line, and the ground signals G1 to Gm can be simultaneously transmitted through a single line.
FIG. 2 is a cross-sectional schematic view of the probe card of the semiconductor test apparatus of FIG. 1. The probe card of FIG. 2 includes a plurality of stacked printed circuit boards 30, 32 and 34.
In FIG. 2, reference numeral 30 denotes printed circuit boards for applying power supply signals P1 and P2 and the ground signal PG. Reference numeral 32 denotes printed circuit boards for applying the command and address signals C1 to Cm and the ground signals CG1 to CGm. Reference numeral 34 denotes printed circuit boards for applying the data input/output signals IO1 to IOn and the ground signals G1 to Gn. The printed circuit boards are electrically insulated from each other.
FIG. 3 shows one of the ground printed circuit boards of the probe card of FIG. 2.
In FIG. 3, the symbol “o” denote signal through holes, and reference numeral 40 denotes a conductive area. Among the through holes “o”, holes to which the ground signals PG, CG1 to CGm and G1 to Gm are applied are electrically connected to the conductive area 40 of the ground printed circuit board, and holes to which the power supply signals P1 and P2, the command and address signals C1 to Cm, and the data input/output signals IO1 to IOn are applied are electrically insulated from the conductive area 40 of the ground printed circuit board.
As such, while the ground signals PG, CG1 to CGm and G1 to Gm are individually applied to the probe card 14, these ground signals are commonly connected within the probe card 14 prior to be being applied to chips DUT1 to DUT4, regions of which are shown by dotted lines in FIG. 3. As a result, the ground signals PG, CG1 to CGm and G1 to Gn applied to ground pads (not shown) of the chips DUT1 to DUT4 are electrically connected in the probe card.
The common electrical connection of ground signals PG, CG1 to CGm and G1 to Gn within the probe card of the conventional test apparatus can cause problems when the ground signals are applied to the ground pads of the chips of the wafer 18. More specifically, when multiple chips are simultaneously tested at a high operating speed, the multiple test signals thereof having the common ground can create ground noise in the probe card. This ground noise can in turn result in normally operative chips being incorrectly tested as defective chips.